1. Field of the Invention
The present invention relates to a master chip, a semiconductor memory, and a method for manufacturing a semiconductor memory and in particular to a static RAM (SRAM).
2. Description of the Related Art
Generally, SRAM cell includes bistable flip-flop and two transfer transistors. The bistable flip-flop includes a pair of CMOS inverters and stores a logic state. If an energetic particle from environment, such as an alpha particle contained in cosmic rays or emitted from a radioactive atomic contained in materials for LSI package, strikes a depletion region between a channel and a diffusion region in a transistor of the CMOS inverter, electrons and holes may be generated in the depletion region. The generated electrons may be collected in the diffusion region along the boundary of the depletion region. If charge perturbation caused by the collected electrons is sufficiently large, the stored logic state may be reversed. Such phenomenon is commonly referred to as a “soft error”. The soft errors are increased by miniaturization and lowered operating voltages of the SRAM cell. Here, Japanese Patent Laid-Open Publication No. 2003-297954 describes a method for adding a capacitor to a storage node of the SRAM cell to prevent the soft errors. However, the capacitor added to the storage node of the SRAM cell has occupied an additional space. Also, additional masks have been required to manufacture the added capacitor in lithography process. Consequently, complexity in a manufacturing process of the SRAM cell has been increased. Recently, vertical transistor has received much attention since large gate of the vertical transistor increases channel current and enhances device speed. Such vertical transistor also contains the soft error problem.